1. Field of the Invention
The invention relates to direct frequency modulation, and in particular to a phase locked loop frequency synthesizer using dynamic carrying to prevent saturation of sigma-delta modulator thereof.
2. Description of the Related Art
FIG. 1 shows a conventional phase locked loop synthesizer 100 with a sigma-delta modulator for modulating a modulus. The phase locked loop synthesizer 100 comprises a phase-frequency detector 101, a charge pump 102, a loop filter 103, a voltage controlled oscillator (VCO), a multi-modulus divider 105, a sigma-delta modulator 106 and a channel selector 107. In direct frequency modulation system, transmitting data TD or baseband modulation data is coupled to the sigma-delta modulator 106. Signal m(t) is the sum of the transmitting data TD (or modulation data) and a DC value of a signal N_fractional. The signal N_fractional corresponds to channel information, having different DC value corresponding to different channels. Control signal Sc generated by the sigma-delta modulator 106 and a signal N_integer are summed and sent to the multi-modulus divider 105 to modulate the modulus Nmod used to divide the output carrier signal frequency of the voltage controlled oscillator 104.
FIGS. 2A to 2D show relationships of sigma-delta modulator (SDM) input DC values with respect to channels in GSM, DCS and PCS modes. After normalization, the SDM input DC value has a minimum of 0 and a maximum of 128/130 (about 0.9846), for GSM mode with reference frequency 26 MHz and channel width 200 KHz. To satisfy every channel specification in GSM, DCS or PCS mode, SDM input DC value must be close to 0 and 1. Referring to FIG. 1, the signal m(t) is the sum of the transmitting data TD and the signal N_fractional. The amplitude of the transmitting data is generally amplified by a compensation filter (not shown in FIG. 1). Thus, the amplitude of the signal m(t), after normalization, may more easily exceed 1 (a threshold) or fall below 0. The SDM input DC value above the threshold or below 0 cannot be represented by the sigma-delta modulator. In other words, such SDM input DC values saturate the sigma-delta modulator, resulting in incorrect function. FIG. 3 illustrates the SDM saturation problem described.